Logic gate function
AXI-Lite bus characteristics, usage
Concept about interrupt
DRAM statements
Verilog blocking/nonblock
Amdahl’s law
Cache organization
Average memory access time
HLS loop unroll
Data hazard – identify data hazard, and its solution
Address decoding
accelerator execution model and programming sequence
AXI master performance – burst length, outstanding request
SRAM model
Load-to-Use hazard elimination
